This invention relates to a semiconductor memory device having a redundancy circuit, and more particularly to a semiconductor memory device in which a defective word line can be replaced by a spare word line.
With the development of the process technology on the semiconductor substrate, the sizes of elements constructing a semiconductor memory device are dramatically reduced. With the miniaturization of the elements, the processing pitch of wirings in the semiconductor memory device becomes smaller. As a result, the rate of occurrence of defects for each unit area due to deterioration of the retention characteristic of memory cells and the short-circuit of wirings caused by a fluctuation in the process and dusts in the clean room in which the process is effected is increased.
Further, with an increase in the capacity of the semiconductor memory device, the chip area tends to become large. For this reason, the probability that the defect occurs in the semiconductor memory device becomes higher. Therefore, a redundancy circuit for compensating for the defect is provided in the semiconductor memory device. The yield of the memory device production is enhanced by replacing the defect circuit with the redundancy circuit, as required.
However, the defect compensating circuit such as the redundancy circuit increases the chip area. Particularly, the redundancy memory cell increases the chip area.
FIG. 1 shows a conventional semiconductor memory device, for example, a dynamic random access memory (DRAM) and shows the arrangement of a memory cell array and a redundancy memory cell array. In this example, one redundancy memory cell array 12 is arranged for four memory cell arrays 11a to 11d each having 256 word lines. A defective word line occurring in the memory cell arrays 11a to 11d is replaced by a spare word line in the redundancy memory cell array 12. The total number of word lines in the four memory cell arrays is 256.times.4=1024 and a 10-bit address signal is necessary to separately designate them. In the address signal, the upper eight bits are supplied to row decoders 13a to 13d and a total of 256 word line group selecting signals MWL are output from the row decoders 13a to 13d. A word line group of four adjacent word lines is selected by one of the word line group selecting signals MWL and one of the four word lines is selected by common word line identification signals WSn (n=0 to 3) which are generated by the low-order 2 bits of the address signal. The word line group selecting signals MWL are supplied to a plurality of word line driving circuits (WD) 16n (n=0 to 255) provided in the memory cell arrays 11a to 11d.
The common word line identification signals WSn cause word line selecting signal generation circuits (WSSG) 14a to 14d and 15 provided for the memory cell array 11a to 11d and redundancy memory cell array 12 to generate signals WDRn (n=0 to 3) and signals SWDRn (n=0 to 3). The signals WDRn are supplied to the plurality of word line driving circuits 16n (n=0 to 255) which are provided 64 for each of the memory cell arrays 11a to 11d and the signals SWDRn are supplied to a plurality of word line driving circuits 17n (n=0 to 63) provided for the redundancy memory cell array 12. One of the word lines selected by the signals WDRn among the four-word line group selected by the word line group selecting signal MWL is driven by a corresponding one of the word line driving circuits 16n.
FIG. 2 shows an example of a circuit of the row decoder 13a. The row decoder includes a plurality of AND circuits 20 and each of the AND circuits 20 outputs the logical AND of a specified combination of eight pairs of address signals A2, /A2, to A9, /A9 as one of the signals MWLn (n=0, 1, 2, 3, . . . ).
FIG. 3 shows one example of the word line selecting signal generation circuit (WSSG). The word line selecting signal generation circuit includes a plurality of AND circuits 21. Each of the AND circuits 21 outputs the logical AND of a block selection signal BS generated by the most significant 2 bits of the address signal and a corresponding one of the signals WSn (n=0 to 3) as one of the signals WDRn (n=0 to 3) so as to activate only one of the four memory cell arrays.
FIG. 4 shows one example of the word line driving circuit (WD). The word line driving circuit includes a plurality of AND circuits 22. The AND circuits 22 drive the word lines WLn (n=0 to 3) according to the logical AND of one word line group selecting signal MWL commonly supplied to the four word lines and the four signals WDRn (n=0 to 3).
In the redundancy memory cell array 12 shown in FIG. 1, spare word line group selecting signals SMWL corresponding to the word line group selecting signals MWL are generated by address coincidence detectors (ACD) 18n (n=0 to 3) for detecting the coincidence between the addresses. The address coincidence detectors 18n store addresses of the word line group selecting signals MWL containing defective word lines by use of nonvolatile memory elements such as fuses which can be blown by laser after testing the device. If the upper 8 bits of the address which is supplied to access the memory cell array coincide with the address stored in the ACD, the spare word line group selecting signal SMWL is activated. In this example, since the four address coincidence detectors are used, four defective portions can be compensated for. As the signal SWDRn for selecting one of the four word lines in the selected group, the same signal out of four SWDRn's is selected irrespective of whether or not the word line is replaced by the spare word line. That is, the replacement is performed by activating one of the spare word line selecting signal SMWL instead of the word line selecting signal MWL to which the defective word line belongs. Therefore, the replacement control can be relatively easily effected.
However, with the above method, four word lines are replaced as one unit for one defective word line and if the number of word lines to be replaced independently is increased, it becomes necessary to provide an extremely large number of spare word lines. As, the number and the area of redundancy memories increase as the number of spare word lines increases, the increase of chip area becomes a problem.